1. Field of the Invention
The present invention relates to an image processing method, an image processing apparatus, and a program for executing that image processing method. In particular, the present invention relates to an image processing method and image processing apparatus having a method for controlling load balancing of PDL processing and RIP processing, and a program for executing that image processing method.
Here, PDL processing is processing that analyzes a Page Description Language and generates a display list. RIP processing is processing that renders the display list as bitmap data using a Raster Image Processor.
2. Description of the Related Art
In parallel processing or pipeline processing of PDL processing and RIP processing in convention print processing using a plurality of CPUs, there are instances of load unbalancing in which (1) a load unbalance occurs according to a drawing area during RIP processing, and (2) a load unbalance occurs between PDL processing and RIP processing.
As a result of that load unbalancing, there is the problem that even if parallel processing is performed, the speed of processing is limited by the slower processing, so that optimal parallel processing or pipeline processing cannot be performed.
The following sorts of proposals have been made to address such problems.
In order to address problem (1), in Japanese Patent Laid-Open No. 10-52950, when generating a DL from PDL data that has been input, the processing load of each drawing area is predicted from the PDL data, and a load correction value is generated. By assigning a region of a drawing area to a plurality of drawing processing units such that the loads are balanced, an attempt is made to address the problems.
In order to address problem (2), in Japanese Patent Laid-Open No. 2005-63027, a selection is made of whether the drawing processing of each processor is set to be processing of rendering to a bitmap (bitmap rendering), or processing (empty drawing) of only updating drawing parameters (vector information). Herein, it is proposed to balance the load of drawing processing on a plurality of processors by this selection.
However, with the above-described conventional techniques, there are problems as follows.
First, in Japanese Patent Laid-Open No. 10-52950, a correction value is generated at the same time as generating a DL, but this correction value generation itself introduces overhead, and there is a possibility that this will reduce the overall print processing capability. In the case of simple data, that overhead is not particularly large, but as the complexity of the data increases, the time required to generate a correction value is expected to increase. Also, there is no description indicating that an accurate processing time cannot be predicted for CPU assignment when there are a plurality of CPUs that perform PDL processing or RIP processing.
On the other hand, in Japanese Patent Laid-Open No. 2005-63027, because interpreter processing of the same PDL data is performed in parallel by a plurality of processors (CPUs), unnecessary processing (empty drawing of a page in which drawing is not performed as a result: PDL processing is also performed) occurs. Also, in Japanese Patent Laid-Open No. 2005-63027, because a memory area in which data is held when performing PDL processing is necessary for each processor (CPU), the amount of memory used is large.